In the last few decades there has been a drastic development in the field of microelectronic, particularly in the field of integrated circuits. Circuit density in the order of hundreds of millions of interconnected circuits has prompted the introduction of new techniques for automatically designing and testing the integrated circuits. In today's environment, with the advent of VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale Integration) it is imperative more than ever that a chip to be manufactured be designed without any error. It is just as important that such chips be tested thoroughly and easily to weed out any defective chip.
Techniques for testing integrated circuits have evolved over the years, and the impact of testing on the chip design has grown in importance. It is no longer possible to design an integrated circuit chip without due consideration of its testing aspect. This approach is known as Design for Testability.
A difficult problem encountered while making a chip ever more testable is a trend in industry to merge logic and memories onto a single chip. The problem is further complicated by the logic surrounding the memory from all sides; hence, its name embedded memory or array. Techniques had to be developed to account for this trend, which prompted the introduction of scan designs, well known in the art. By placing scan chains at the boundaries between the logic and the embedded arrays, it is possible to segregate the logic from the memory in order that they be tested separately.
Memories have evolved over the years from stand-alone to embedded and from single port to multi-port arrays. A typical architecture of a circuit with an embedded multi-port memory is illustrated in FIG. 1.
A multi-port RAM embedded in logic (40) is typically provided with multiple write/reset ports and multiple read ports, each capable of accessing either a section or the entire storage space of the RAM. A simple conventional RAM is provided with a write port formed by a plurality of address pins (Ao, . . . , Aj), a plurality of data pins (Do, . . . , Di) equal to the word length, and a write clock pin (W_clk), serving as inputs. A bank of setup latches (30) controls the address and input data pins of the embedded RAM through combinatorial logic blocks (25). A pulse on the write clock pin (W_clk) of the RAM stores data on the input data pins (Do, . . . , Di) at a word location specified by the address pins (Ao, . . . , Aj). (For sake of simplicity, timing-related issues such as hold time unless specifically pointed out will be ignored). A read port, on the other hand, includes a plurality of address pins (Ao, . . . , Aj) and a read-enable pin (R_en) as its inputs, and a number of data output pins (Do, . . . , Di) equal to the word length. When a read port is read-enabled, the bit values of the word selected by the address on the read port address pins become available at the output data pins and are latched in read-capture latches (10) by a subsequent pulse on the read-capture clock. When the read port is read-disabled, the output pins take a so-called read-off value which depends on the physical design of the RAM for a specific technology. The read-off value is either a logic 0, 1, or X (i.e., a condition wherein neither a logic 1 nor a 0 is guaranteed).
Still referring to FIG. 1, logic (40) is provided with a plurality of input pins (Plo, . . . , Plp) and clock signal pins (CLKo, . . . , CLKk) as primary inputs, and plural output pins (POo, . . . , POq) as primary outputs. The clock distribution and gating logic (15) prompt clocks (CLKo, . . . , CLKk) and a subset of the inputs (Plo, . . . , Plp) to generate control signals to activate the setup latches (30), the write clock pins (W—clk) of the RAM's write ports, the read-capture signals to the read-capture latches (12) and local clocks regulating the sequential elements (20).
Oftentimes, combinatorial logic as well as sequential elements (20) are present in the ‘upstream’ and ‘downstream’ logic from the embedded RAM. Circuits using multiple clocks (e.g., CLKo, . . . , CLKk) are provided with a clock distribution and gating logic (15) that includes sequential elements as well. Other circuits, having combinatorial logic blocks (25), are positioned between the setup latches (30), the embedded multi-port RAM and the read-capture latches (12).
In a full scan design, as illustrated in FIG. 2, an embedded RAM is directly controlled by the setup latches (30, in FIG. 1) and read-capture latches (12, in FIG. 1) which are configured as scan latches (50). Typically, they are linked to form a chain (or chains) for scan shift (load and unload) operations. The scan-load operation sets the scan latches to the desired values and the scan-unload shifts out the values stored in the latches.
In a partial-scan design, as illustrated in FIG. 3, the setup latches (30, In FIG. 1) are configured as scan latches (50) directly controlling the data and address inputs of the RAM, except for the read-capture latches (12, in FIG. 1). In a non-scan design, all the latches and memory elements are configured in a non-scannable configuration and are not directly accessible through the primary inputs and outputs.
A write/read port must have as its inputs a plurality of address pins, a plurality of data input pins equal to the word length, a write clock pin and a read enable pin, and a plurality of data output pins equal to the word length as its outputs.
A write/read port combines the functions of a write port with those of a read port, using a single set of address input pins. When a pulse appears at the write clock pin while the port is read-enabled, data on the data input pins becomes available at the output pins during and after the write clock pulse, provided that the port is still read-enabled while the address inputs remain unchanged. Such an operation is commonly referred to as write-through mode. It can also be advantageously configured having separate write and read ports.
A reset port has as inputs a plurality of data input pins equal to the word length and a write clock pin. During and following a pulse being applied to the write clock pin of a reset port, data on the input pins is written into all words in the RAM. When more than one write/reset port attempts to simultaneously write on the same word, it is customary that the design and technology dictate that one of the ports dominate the write operation. Accordingly, the bits that prompt the two simultaneous write operations attempting to write different values are set in a predetermined manner. In the present model, the dominant port always appears before the dominated port(s). When such specification is not available from the designer and/or technology sources, unknown values are assumed for the bits having conflicting values on simultaneous writes. A RAM provided with a read-capture built-in capability holds the read data available at the output pins until the next read operation is performed. Such a RAM configuration is commonly referred to as read-hold.
Deterministic Test Pattern Generation
Referring now to the test circuits that include (an) embedded RAM(s), it is known in the art that in a conventional deterministic automatic test pattern generation (ATPG), a target fault is selected for processing in the upstream or downstream logic from the embedded RAM, including at the input and output pins of the RAM. A test sequence is then generated if the target fault is testable. This test sequence is transferred to another process, referred to as test subsumation, which identifies similar test sequences and merges them into one. Test sequences resulting from the subsumation process are significantly more compact, with unspecified input pins filled with random values, and are sent to the fault simulation process for simulation against undetected faults.
Deterministic ATPG process typically employs one or more deterministic test generation algorithms such as PODEM described e.g., by P. Goel, “PODEM-X: An automatic test generation system for VLSI logic structures”, published in the Proceedings of the 18th Design Automation Conference, pp. 260-268, 1981, and “An implicit enumeration algorithm to generate tests for combinatorial logic circuits”, IEEE Trans. Computers, C-30 (3): 215-222, 1981. A second ATPG algorithm referred to as FAN is described by H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms”, IEEE Transactions of Computers, C-32 (12): 1137-1144, 1983, and in a textbook by H. Fujiwara, “Logic testing and design for testability”, MIT Press, 1985.
Deterministic ATPG algorithms generally include three distinct process components: fault excitation, path sensitization, and state or logic justification. The distinguishing characteristic of each ATPG algorithm resides in how the execution of these three tasks differs in the order of processing to maximize the efficiency of the algorithm.
A typical deterministic test sequence exercises only selected read ports that are required for testing the target fault. Therefore, when the test sequence is applied, read ports having a predetermined data at their output pins (or at some other read ports) are set to read from words that were already written with a specific or desired data. It results that non-utilized read ports generate an X value at the respective outputs, reducing the efficiency of the test sequences.
By way of example, and with reference to FIG. 4, there is shown an embedded RAM consisting of one WRITE port and four READ ports, wherein R_en (Reset enable) pins of the read ports and the last two read address pins of each read port are “hard wired”. The intent is to generate a deterministic test sequence which detects a stuck-at-0 fault condition, e.g., at the d0 output line of Port 2. A typical deterministic test generation algorithm (such as PODEM or FAN) initiates the test pattern generation process by setting a fault excitation value of 1 on the same d0 output line where the target fault is located. The algorithm backtraces (i.e., traverses in the direction from an output towards an input) through the RAMs Port 2, knowing that the port is a READ port and its R_en pin is ON (since it is attached to a 1). A read address is then selected, assuming all 1s on the A0-2 pins of Port 2. These assumed 1s at the A0-2 pins of Port 2 are justified by loading the setup scan latches, which directly set the pins to 1. Next, in order to ensure that the Port 2 D0 output data pin is at 1 (to distinguish the fault condition of stuck-at-0), it requires a write operation to set the data bit D0 of the RAM to 1 at selected all-1 word address pins. These write address and data pins are set by loading 1s on the setup scan latches that directly control the A0-4 address pins. The same is done for the D0 data pin of Port 1. Once the setup scan latches are loaded with the desired address and data values, a PULSE on the write clock controlling the W_-clk pin of Port 1 writes a data 1 into data bit D0 at the selected word (A0-4=11111) producing a 1 at the output pin D0 of Port 2 in the fault-free circuit. Now the fault-free circuit has a 1 on the data output pin D0 of Port 2, while the same output pin has the stuck-at-0 condition in the faulty-circuit. Therefore, the fault-effect 1/0 (for fault-free-value/faulty-value) appears at the input of the read-capture latch, whose data input is fed by the D0 output pin of Port 2. A pulse on this read-capture latch captures the fault-effect 1/0 into its memory. A subsequent scan shift operation shifts the fault-effect out for observation.
The resulting test sequence of prior art, referred to as Test Sequence 1, is described as follows with reference to the waveforms illustrated in FIG. 5:
Test Sequence 1:
Pattern 1: (Type=Scan-Load)                Load the setup latches such that A0-4 and D0 of Port 1, and A0-2 of Port 2 are all at 1        
Pattern 2: (Type=Pulse Clock)                Apply a PULSE to the write clock.        
Pattern 3: (Type=Pulse Clock)                Apply a PULSE to the read/capture clock.        
Pattern 4: (Scan-Unload)                Shift out the data captured in the Read-Capture latches        
When the Test Sequence 1 is applied, it generates a miscompare (i.e., the fault-free circuit signal value is different from the faulty circuit signal value) on data bit D0 of Port 2 located in the scan shift-out data stream. Pattern 1 is a test data input pattern of scan-load type which loads the setup latches controlling the A0-4 address and D0 data pins of Port 1, along with those controlling A0-2 address pins of Port 2, setting them all to 1. After applying this pattern, the circuit is conditioned as shown in FIG. 4, into a write-ready state with the RAM write operation singled out by a write clock.
Pattern 2 is a test data input pattern of a pulse clock type which specifies applying a pulse to the write clock input. After applying Pattern 2, data bit D0 at the word address 11111 is set to 1. The remaining data bits at the same address are assigned random values since the scan load by Pattern 1 did not set up the scan latches controlling the D1-3 pins of Port 1 with specified input values. After applying Pattern 2, a fault-effect 1/0 appears on the data output pin 0 of Port 2 as well as on line d0.
Pattern 3 is a test data input of pulse clock type which locks the fault-effect 1/0 into the associated latch in the bank of read-capture latches's shown in FIG. 4. After applying Pattern 3, the fault-effect 1/0 is locked by the read-capture scan latch which data input is directly fed by the D0 output pin of Port 2.
Pattern 4 is a test data input of scan unload, which instructs shifting out the scan latch contents. After applying Pattern 4, the 1/0 fault-effect from the data output pin D0 of Port 2 is observed in the scan-out data stream.
Note that lines A0-2 of Port 1 and Port 2 can be set with any combination of 0s and 1s, provided that the read and write addresses are identically set up in Pattern 1.
FIG. 5 shows the waveforms applicable to the circuit shown in FIG. 4 when Test Sequence 1 is applied. The vertical lines referenced by A, B, C, D and E at the near-bottom of FIG. 5 denote the specific time of each signal transition. Vertical line A indicates the moment immediately after applying Pattern 1, with the A0-4 address and D0 pins of Port 1, along with the A0-2 address pins of Port 2 set to the desired values. Vertical line B indicates the instant when Pattern 2 is applied. Data output D0 pin of Port 2 in the fault-free circuit is set to 1. The signal waveform on the same D0 output pin of Port 2 of a defective circuit is not shown in FIG. 5, since it remains permanently at 0 to reflect a stuck-at-0 fault condition. Vertical lines C and D indicate the beginning and the end of the read-capture clock pulse, respectively, when Pattern 3 is applied, which locks the 1/0 fault-effect into the associated read-capture scan latch. Vertical line E indicates the instant when Pattern 4 is applied, which scans-out the scan latch data. The 1/0 fault effect is observed in the scan-out data stream.
Similarly, conventional deterministic ATPG algorithms generate the following Test Sequences 2, 3, and 4 for stuck-at-0 faults on the d0 output lines of Ports 3, 4, and 5, respectively:
Test Sequence 2:
Pattern 1: (Type=Scan Load)                Load the Setup latches so that A0-3 and D0 of Port 1 are at 1, A4 is at 0, and A0-2 of Port 3 are at 1.        
Pattern 2: (Type=Pulse Clock)                Apply a PULSE to the write clock.        
Pattern 3: (Type=Pulse Clock)                Apply a PULSE to the read/capture clock.        
Pattern 4: (Type=Scan Unload)                Shift out the data captured in the Read-Capture latches.Test Sequence 3:        
Pattern 1: (Type=Scan Load)                Load the Setup latches so that A0-2, A4 and D0 of Port 1 are at 1, A3 is at 0, and A0-2 of Port 4 is at 1.        
Pattern 2: (Type=Pulse Clock)                Apply a PULSE to the write clock.        
Pattern 3: (Type=Pulse Clock)                Apply a PULSE to the read/capture clock.        
Pattern 4: (Type=Scan Unload)                Shift out the data captured in the Read-Capture latchesTest Sequence 4:        
Pattern 1: (Type=Scan Load)                Load the Setup latches so that A0-2 and D0 of Port 1 are at 1, A3-4 are at 0, and A0-2 of Port 5 are at 1.        
Pattern 2: (Type=Pulse Clock)                Apply a PULSE to the write clock.        
Pattern 3: (Type=Pulse Clock)                Apply a PULSE to the read/capture clock.        
Pattern 4: (Type=Scan Unload)                Scan-out the data captured in the read-capture latches        
Test Sequences 1, 2, 3, and 4 can be applied in any order to form a test set of 16 test patterns. These four test sequences share the same pattern flow, namely: scan load (Pattern 1)->Pulse clock (Pattern 2)->Pulse clock (Pattern 3)->scan unload (Pattern 4). Among the many characteristics commonly known to practitioners generating deterministic test patterns, there are two distinct concerns associated with those deterministically generated test sequences for circuits having embedded multi-port RAMs, such as prior art Test Sequences 1, 2, 3, and 4.
One concern is that the test sequences cannot be merged into each other with prior art methods in order to reduce the overall test set size lower than 16 patterns. This is caused by a conflicting setup between the A3-4 pins of Port 1 set by Pattern 1 in all four test sequences. For example, a scan load by Pattern 1 in Test Sequence 1 sets A3-4 pins of Port 1 to 1, while the scan load Pattern 1 in Test Sequence 2 sets A3 of Port 3 to 1 and its A4 to a 0, in Test Sequence 3 with A3 pin of Port 1 to 0 A4 pin to 1, and in Test Sequence 4 with the A3-4 pins of Port 1 to 0. Therefore, the four different setups of the A3-4 address pins of Port 1 cannot be achieved with a single scan load operation. Consequently, known test set compaction methods (reducing the size of a test data set) are unable to reduce the overall number of patterns to less than 16.
A second concern exists when test sequences such as Test Sequences 1, 2, 3, and 4 are applied when only a few selected read ports are set to read from predetermined written words in the RAM. For example, Test Sequence 1 sets Port 2 to read from a written word (A0-4=11111), leaving Ports 3, 4, and 5 read addresses unspecified and causing these ports to read from words which have not yet been written. Test Sequence 2 sets Port 3 to read from a written word (A0-4=11110), leaving Ports 2, 4, and 5 read addresses unspecified. The unused read ports produce unknown values at the outputs of these read ports when the test sequences are applied. These unknown values limit the efficiency of the test sequences, which is measured by the number of faults detected.
Related patents and publications to the present invention are:
U.S. Pat. No. 5,499,249 describes a method for automatic test generation for designs with embedded RAMs when they are surrounded, either partially or fully, by sequential design elements such as non-scan flip-flops, by using the functional models of the RAMs. The deterministic test patterns propagate fault effects in the upstream logic through the embedded RAMs to the observation points (either primary outputs or scan measure latches) and justify required signal values for testing faults in the downstream logic through the embedded RAMs. However, the patent does not guarantee that all outputs of multi-port embedded RAMs have specified values. When the method of this patent is applied, it generates test sequences equivalent to Test Sequences 1 to 5, with outputs of many read ports left in an unknown state prior to read-capture. Therefore, it does not overcome the problem of having unknown RAM output values when these test sequences are applied. Further, this method is not capable of exploring different structural configurations of embedded RAMs and making a deterministic test more efficient by ensuring all RAMs to have known output values. In summary, the aforementioned patent is not capable of solving the deterministic test pattern generation problem which leaves the embedded RAM (in multi-port configurations) output signals in an unknown state when deterministically-generated test sequences are applied.
U.S. Pat. No. 5,442,640 describes using randomly-generated patterns to test the logic (post-logic) fed by embedded arrays such as RAMs. Unless the entire space of RAMs is written when randomly-generated patterns are applied, many of the RAM outputs do not take a known value. This causes the RAM outputs feeding the post-logic circuits to unspecified values, limiting the effectiveness of the tests. This method requires long test cycles and is not able to test pre-logic circuits.
U.S. Pat. No. 5,331,643 to Smith et al. describes a method of having sections of the scan registers feeding the address pins of embedded arrays to be bypassed so that embedded arrays can be tested effectively with pseudo-random test data. The bypassed sections of the scan registers are connected to an address stepper mechanism which insures complete coverage throughout the range of the embedded array. The address stepper mechanism uses either a stepping counter or a linear feedback shift register or similar mechanism. This ensures that each cell address in the array is provided with known pseudo-random data at the beginning of a test. As with all random pattern tests, this method requires lengthy test cycles and lacks the ability to test faults on the address and read/write signals, compared to deterministic test generation methods.
A paper by L. C. Wang and M. S. Abadir, “Test Generation based on High Level Assertion Specification for PowerPC™ Microprocessor Embedded Arrays”, Journal of Electronic Test: Theory and Application, Vol.13, No. 2, October. 1998, p121-35, Kluwer Academic Publishers. This paper describes a test generation method for embedded arrays using a technique called assertion, which is commonly used in formal verification. It applies the assertion technique with the functional model of embedded arrays to generate test. It does not show how the test generation works with embedded multi-port RAMs.
An article by M. E. Levitt, S. Nori, S. Narayanan, G. P. Grewal, L. Youngs, A. Jones, G. Billus, and S. Paramanandam, “Testability, debuggability, and manufacturability features of the UltraSPARC-I™ microprocessor”, Proceedings of the International Test Conference, October 1995, IEEE.
An article by M. E. Levitt, “Designing UltraSparc™ for Testability”, Design and Test of Computers, Vol. 14, No. 1, March 1997, IEEE.
An article by G. Billus and L. Youngs, “Test of the UltraSPARC-I Microprocessor Embedded Memories, TLBs, and Register Files”, Texas Instruments Technical Journal, Vol. 13, No. 3, May-June 1996, pp. 101-110, Texas Instruments Inc
The above three publications have a section on embedded-array testing, with little detailed information on how it is achieved. No explanation is given how a custom SRAM test mode is used to facilitate a required test, particularly, where 400 gates and 100 flip-flops are used in the implementation of the test mode. Further, these publications do not describe the generation of test sequences used for the SRAM test mode altogether.